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GS816272Cc-333/300/250 256k x 72 18mb s/dcd sync burst srams 333 mhz ? 250 mhz 2.5 v or 3.3 v v dd 2.5 v or 3.3 v i/o 209-bump bga commercial temp industrial temp preliminary rev: 1.00 9/2004 1/31 ? 2004, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. features ? ft pin for user-configurable flow through or pipeline operation ? single/dual cycle deselect selectable ? ieee 1149.1 jtag-compatible boundary scan ? zq mode pin for user-selectable high /low output drive ? 2.5 v or 3.3 v +10%/?10% core power supply ? lbo pin for linear or interleaved burst mode ? internal input resistors on mode pins allow fl oating mode pins ? default to scd x18/x36 in terleaved pipeline mode ? byte write (bw ) and/or global write (gw ) operation ? internal self-timed write cycle ? automatic power-down fo r portable applications ? jedec-standard 209-bump bga package functional description applications the GS816272Cc is an 18,874,368-bit high performance synchronous sram with a 2-bit burst address counter. although of a type originally developed for leve l 2 cache applications supporting high performance cpus, the devi ce now finds application in synchronous sram applications, ra nging from dsp main store to networking chip set support. controls addresses, data i/os, chip enable (e1 ), address burst control inputs (adsp , adsc , adv ), and write control inputs (bx , bw , gw ) are synchronous and are controlled by a positive-edge-triggered clock input (ck). output enable (g ) and power down control (zz) are asynchronous inputs. burst cycles can be initiated with either adsp or adsc inputs. in burst mode, subs equent burst addresses are generated internally an d are controlled by adv . the burst address counter may be configured to count in either linear or interleave order with the linear burst order (lbo ) input. the burst function need not be used. new addresses can be loaded on every cycle with no degradation of chip performance. flow through/pipeline reads the function of the data output regist er can be controlled by the user via the ft mode . holding the ft mode pin low places the ram in flow through mode, causing output data to bypass the data output register. holding ft high places the ram in pipeline mode, activating the rising-edge-trigg ered data output register. scd and dcd pipelined reads the GS816272Cc is an scd (single cycle deselect) and dcd (dual cycle deselect) pipelined synchronous sram. dcd srams pipeline disable commands to the same degree as read commands. scd srams pipeline deselect commands one stage less than read commands. scd rams begin turni ng off their outputs immediately after the deselect command has been captured in the input registers. dcd rams hold the deselect comma nd for one full cycle and then begin turning off their outputs just after the second rising edge of clock. the user may configure th is sram for either mode of operation using the scd mode input. byte write and global write byte write operation is performed by using byte write enable (bw ) input combined with one or more individual byte wr ite signals (bx ). in addition, global write (gw ) is available for writing all bytes at one time, regardless of the by te write control inputs. flxdrive? the zq pin allows sele ction between high drive strength (zq low) for multi-drop bus applicati ons and normal drive st rength (zq floating or high) point-to-point applicat ions. see the output driver characteristics chart for details. sleep mode low power (sleep mode) is attained through the assertion (high) of the zz signal, or by stopping the cloc k (ck). memory data is retained during sleep mode. core and interface voltages the GS816272Cc operates on a 2.5 v or 3.3 v power supply. all input are 3.3 v and 2.5 v compa tible. separate output power (v ddq ) pins are used to decouple output noise from the internal circuits and are 3.3 v and 2.5 v compatible. parameter synopsis -333 -300 -250 unit pipeline 3-1-1-1 t kq tcycle 2.8 3.0 2.8 3.3 3.0 4.0 ns ns curr 545 495 425 ma flow through 2-1-1-1 t kq tcycle 4.5 4.5 5.0 5.0 5.5 5.5 ns ns curr 380 345 315 ma
GS816272Cc-333/300/250 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 9/2004 2/31 ? 2004, gsi technology GS816272C pad out?209-bump bga?top view (package c) 1234567891011 a dqg dqg a e2 adsp adsc adv e 3adqbdqb b dqg dqg b cb gnc b ab bb fdqbdqb c dqg dqg b hb dnce 1ncb eb adqbdqb d dqg dqg v ss nc nc g gw nc v ss dqb dqb e dqpg dqpc v ddq v ddq v dd v dd v dd v ddq v ddq dqpf dqpb fdqcdqc v ss v ss v ss zq v ss v ss v ss dqf dqf g dqc dqc v ddq v ddq v dd mch v dd v ddq v ddq dqf dqf h dqc dqc v ss v ss v ss mcl v ss v ss v ss dqf dqf j dqc dqc v ddq v ddq v dd mcl v dd v ddq v ddq dqf dqf k nc nc ck nc v ss mcl v ss nc nc nc nc l dqh dqh v ddq v ddq v dd ft v dd v ddq v ddq dqa dqa m dqh dqh v ss v ss v ss mcl v ss v ss v ss dqa dqa n dqh dqh v ddq v ddq v dd scd v dd v ddq v ddq dqa dqa p dqh dqh v ss v ss v ss zz v ss v ss v ss dqa dqa r dqpd dqph v ddq v ddq v dd v dd v dd v ddq v ddq dqpa dqpe t dqd dqd v ss nc nc lbo nc nc v ss dqe dqe u dqddqdncaaaaancdqedqe vdqddqdaaaa1aaadqedqe w dqd dqd tms tdi a a0 a tdo tck dqe dqe rev 10 11 x 19 bump bga ? 14 x 22 mm 2 body ? 1 mm bump pitch
GS816272Cc-333/300/250 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 9/2004 3/31 ? 2004, gsi technology bpr1999.05.18 GS816272C bga pin description symbol type description a 0 , a 1 i address field lsbs and addr ess counter preset inputs. a i address inputs dq a dq b dq c dq d dq e dq f dq g dq h i/o data input and output pins b a , b b , b c ,b d, b e , b f , b g ,b h i byte write enable for dq a , dq b , dq c , dq d, dq e , dq f , dq g , dq h i/os; active low nc ? no connect ck i clock input signal; active high gw i global write enable?writes all bytes; active low e 1, e 3 i chip enable; active low e 2 i chip enable; active high g i output enable; active low adv i burst address counter advance enable; active low adsp , adsc i address strobe (processor, cache controller); active low zz i sleep mode control; active high ft i flow through or pipeline mode; active low lbo i linear burst order mode; active low scd i single cycle deselect/dual cycle deselect mode control mch i must connect high mcl must connect low bw i byte enable; active low zq i flxdrive output impedance control (low = low impedance [high drive], high = high impedance [low drive]) tms i scan test mode select tdi i scan test data in tdo o scan test data out tck i scan test clock v dd i core power supply v ss i i/o and core ground v ddq i output driver power supply
GS816272Cc-333/300/250 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 9/2004 4/31 ? 2004, gsi technology GS816272C block diagram a1 a0 a0 a1 d0 d1 q1 q0 counter load dq dq register register dq register dq register dq register dq register dq register dq register d q register d q register a0?an lbo adv ck adsc adsp gw bw e 1 ft g zz power down control memory array 36 36 4 a qd dqx1?dqx9 36 36 note: only x36 version shown for simplicity. scd 36 36 b a b b b c b d
GS816272Cc-333/300/250 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 9/2004 5/31 ? 2004, gsi technology note: there are pull-up devices on the zq, scd, and ft pins and a pull-down device on the zz pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables. burst counter sequences bpr 1999.05.18 mode pin functions mode name pin name state function burst order control lbo l linear burst h interleaved burst power down control zz l or nc active h standby, i dd = i sb single/dual cycle deselect control scd l dual cycle deselect h or nc single cycle deselect flxdrive output impedance control zq l high drive (low impedance) h or nc low drive (high impedance) note: the burst counter wraps to initial state on the 5th clock. note: the burst counter wraps to initial state on the 5th clock. linear burst sequence a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 10 11 00 3rd address 10 11 00 01 4th address 11 00 01 10 interleaved burst sequence a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 00 11 10 3rd address 10 11 00 01 4th address 11 10 01 00
GS816272Cc-333/300/250 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 9/2004 6/31 ? 2004, gsi technology notes: 1. all byte outputs are active in read cycles regar dless of the state of byte write enable inputs. 2. byte write enable inputs b a , b b , b c , and/or b d may be used in any combination with bw to write single or multiple bytes. 3. all byte i/os remain high-z during all write operations regardless of the state of byte write enable inputs. 4. bytes ? c ? and ? d ? are only available on the x36 version. byte write truth table function gw bw b a b b b c b d notes read h h x x x x 1 read hlhhhh1 write byte a h l l h h h 2, 3 write byte b h l h l h h 2, 3 write byte c h l h h l h 2, 3, 4 write byte d h l h h h l 2, 3, 4 write all byteshlllll2, 3, 4 write all byteslxxxxx
GS816272Cc-333/300/250 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 9/2004 7/31 ? 2004, gsi technology synchronous truth table operation address used state diagram key 5 e 1 adsp adsc adv w 3 dq 4 deselect cycle, power down none x h x l x x high-z read cycle, begin burst external r l l x x x q read cycle, begin burst external r l h l x f q write cycle, begin burst external w l h l x t d read cycle, continue burst next cr x h h l f q read cycle, continue burst next cr h x h l f q write cycle, continue burst next cw x h h l t d write cycle, continue burst next cw h x h l t d read cycle, suspend burst current x h h h f q read cycle, suspend burst current h x h h f q write cycle, suspend burst current x h h h t d write cycle, suspend burst current h x h h t d notes: 1. x = don?t care, h = high, l = low 2. w = t (true) and f (false) is defined in the byte write truth table preceding 3. g is an asynchronous input. g can be driven high at any time to disable active output drivers. g low can only enable active drivers (shown as ?q? in the truth table above). 4. all input combinations shown above are tested and supported. in put combinations shown in gray boxes need not be used to accom plish basic synchronous or synchronous burst oper ations and may be avoided for simplicity. 5. tying adsp high and adsc low allows simple non-burst synchronous operations. see bold items above. 6. tying adsp high and adv low while using adsc to load new addresses allows simple burst operations. see italic items above.
GS816272Cc-333/300/250 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 9/2004 8/31 ? 2004, gsi technology simplified state diagram first write first read burst write burst read deselect r w cr cw x x wr r wr x x x simple synchronous operation simple burst synchronous operation cr r cw cr cr notes: 1. the diagram shows only supported (tested) synchr onous state transitions. the diagram presumes g is tied low. 2. the upper portion of the diagram assume s active use of only the enable (e1 ) and write (b a , b b , b c , b d , bw , and gw ) control inputs, and that adsp is tied high and adsc is tied low. 3. the upper and lower portions of the diagram together a ssume active use of only the enable, write, and adsc control inputs and assumes adsp is tied high and adv is tied low.
GS816272Cc-333/300/250 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 9/2004 9/31 ? 2004, gsi technology simplified state diagram with g first write first read burst write burst read deselect r w cr cw x x wr r w r x x x cr r cw cr cr w cw w cw notes: 1. the diagram shows supported (tes ted) synchronous state transit ions plus supported transitions that depend upon the use of g . 2. use of ?dummy reads? (read cycles with g high) may be used to make the transition from read cycles to write cycles without passing through a deselect cycle. dummy read cycles increment the address counter just like normal read cycles. 3. transitions shown in grey tone assume g has been pulsed high long enough to turn the ram?s drivers off and for incoming data to meet data input set up time.
GS816272Cc-333/300/250 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 9/2004 10/31 ? 2004, gsi technology note: permanent damage to the device may occur if the absolute maximum ratings are exceeded. operation should be restricted to recomm ended operating conditions. exposure to conditions exceeding the absolute maximum ra tings, for an extended period of time, may affect reliability of this component. absolute maximum ratings (all voltages reference to v ss ) symbol description value unit v dd voltage on v dd pins ? 0.5 to 4.6 v v ddq voltage in v ddq pins ? 0.5 to 4.6 v v i/o voltage on i/o pins ? 0.5 to v ddq +0.5 ( 4.6 v max.) v v in voltage on other input pins ? 0.5 to v dd +0.5 ( 4.6 v max.) v i in input current on any pin +/ ? 20 ma i out output current on any i/o pin +/ ? 20 ma p d package power dissipation 1.5 w t stg storage temperature ? 55 to 125 o c t bias temperature under bias ? 55 to 125 o c power supply voltage ranges parameter symbol min. typ. max. unit notes 3.3 v supply voltage v dd3 3.0 3.3 3.6 v 2.5 v supply voltage v dd2 2.3 2.5 2.7 v 3.3 v v ddq i/o supply voltage v ddq3 3.0 3.3 3.6 v 2.5 v v ddq i/o supply voltage v ddq2 2.3 2.5 2.7 v notes: 1. the part numbers of industrial temperatur e range versions end the character ?i?. un less otherwise noted, all performance spe cifica- tions quoted are evaluated for worst case in the temperature range marked on the device. 2. input under/overshoot voltage must be ? 2 v > vi < v ddn +2 v not to exceed 4.6 v maximum, with a pulse width not to exceed 20% tkc.
GS816272Cc-333/300/250 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 9/2004 11/31 ? 2004, gsi technology v ddq3 range logic levels parameter symbol min. typ. max. unit notes v dd input high voltage v ih 2.0 ? v dd + 0.3 v1 v dd input low voltage v il ? 0.3 ? 0.8 v 1 v ddq i/o input high voltage v ihq 2.0 ? v ddq + 0.3 v1,3 v ddq i/o input low voltage v ilq ? 0.3 ? 0.8 v 1,3 notes: 1. the part numbers of industrial temperatur e range versions end the character ?i?. un less otherwise noted, all performance spe cifica- tions quoted are evaluated for worst case in the temperature range marked on the device. 2. input under/overshoot voltage must be ? 2 v > vi < v ddn +2 v not to exceed 4.6 v maximum, with a pulse width not to exceed 20% tkc. 3. v ihq (max) is voltage on v ddq pins plus 0.3 v. v ddq2 range logic levels parameter symbol min. typ. max. unit notes v dd input high voltage v ih 0.6*v dd ? v dd + 0.3 v1 v dd input low voltage v il ? 0.3 ? 0.3*v dd v1 v ddq i/o input high voltage v ihq 0.6*v dd ? v ddq + 0.3 v1,3 v ddq i/o input low voltage v ilq ? 0.3 ? 0.3*v dd v1,3 notes: 1. the part numbers of industrial temperatur e range versions end the character ?i?. un less otherwise noted, all performance spe cifica- tions quoted are evaluated for worst case in the temperature range marked on the device. 2. input under/overshoot voltage must be ? 2 v > vi < v ddn +2 v not to exceed 4.6 v maximum, with a pulse width not to exceed 20% tkc. 3. v ihq (max) is voltage on v ddq pins plus 0.3 v. recommended operating temperatures parameter symbol min. typ. max. unit notes ambient temperature (com mercial range versions) t a 02570 c2 ambient temperature (industrial range versions) t a ? 40 25 85 c2 notes: 1. the part numbers of industrial temperatur e range versions end the character ?i?. un less otherwise noted, all performance spe cifica- tions quoted are evaluated for worst case in the temperature range marked on the device. 2. input under/overshoot voltage must be ? 2 v > vi < v ddn +2 v not to exceed 4.6 v maximum, with a pulse width not to exceed 20% tkc.
GS816272Cc-333/300/250 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 9/2004 12/31 ? 2004, gsi technology note: these parameters are sample tested. capacitance (t a = 25 o c, f = 1 mh z , v dd = 2.5 v) parameter symbol test conditions typ. max. unit input capacitance c in v in = 0 v 45pf input/output capacitance c i/o v out = 0 v 67pf ac test conditions parameter conditions input high level v dd ? 0.2 v input low level 0.2 v input slew rate 1 v/ns input reference level v dd /2 output reference level v ddq /2 output load fig. 1 notes: 1. include scope and jig capacitance. 2. test conditions as specified with output loading as shown in fig. 1 unless otherwise noted. 3. device is deselected as defined by the truth table. 50% tkc v ss ? 2.0 v 50% v ss v ih undershoot measurement and timing overshoot measurement and timing 50% tkc v dd + 2.0 v 50% v dd v il dq v ddq/2 50 ? 30pf * output load 1 * distributed test jig capacitance
GS816272Cc-333/300/250 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 9/2004 13/31 ? 2004, gsi technology dc electrical characteristics parameter symbol test conditions min max input leakage current (except mode pins) i il v in = 0 to v dd ? 1 ua 1 ua zz input current i in1 v dd v in v ih 0 v v in v ih ? 1 ua ? 1 ua 1 ua 100 ua ft , scd, zq input current i in2 v dd v in v il 0 v v in v il ? 100 ua ? 1 ua 1 ua 1 ua output leakage current i ol output disable, v out = 0 to v dd ? 1 ua 1 ua output high voltage v oh2 i oh = ? 8 ma, v ddq = 2.375 v 1.7 v ? output high voltage v oh3 i oh = ? 8 ma, v ddq = 3.135 v 2.4 v ? output low voltage v ol i ol = 8 ma ? 0.4 v
GS816272Cc-333/300/250 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 9/2004 14/31 ? 2004, gsi technology notes: 1. i dd and i ddq apply to any combination of v dd3 , v dd2 , v ddq3 , and v ddq2 operation. 2. all parameters listed are worst case scenario. operating currents parameter test conditions mode symbol -333 -300 -250 unit 0 to 70c ? 40 to 85c 0 to c ? 40 to 85c 0 to 70c ? 40 to 85c operating current device selected; all other inputs v ih o r v il output open (x72) pipeline i dd i ddq 460 85 470 85 415 80 425 80 350 75 360 75 ma flow through i dd i ddq 320 60 330 60 290 55 300 55 265 50 275 50 ma standby current zz v dd ? 0.2 v ? pipeline i sb 40 50 40 50 40 50 ma flow through i sb 40 50 40 50 40 50 ma deselect current device deselected; all other inputs v ih or v il ? pipeline i dd 85 90 85 90 85 90 ma flow through i dd 60 65 60 65 60 65 ma
GS816272Cc-333/300/250 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 9/2004 15/31 ? 2004, gsi technology notes: 1. these parameters are sampled and are not 100% tested. 2. zz is an asynchronous signal. however, in order to be recogniz ed on any given clock cycle, zz mu st meet the specified setup a nd hold times as specified above. ac electrical characteristics parameter symbol -333 -300 -250 unit min max min max min max pipeline clock cycle time tkc 3.0 ? 3.3 ? 4.0 ? ns clock to output valid tkq ? 2.8 ? 2.8 ? 3.0 ns clock to output invalid tkqx 1.5 ? 1.5 ? 1.5 ? ns clock to output in low-z tlz 1 1.5 ? 1.5 ? 1.5 ? ns setup time ts 1.0 ? 1.0 ? 1.2 ? ns hold time th 0.1 ? 0.1 ? 0.2 ? ns flow through clock cycle time tkc 4.5 ? 5.0 ? 5.5 ? ns clock to output valid tkq ? 4.5 ? 5.0 ? 5.5 ns clock to output invalid tkqx 2.0 ? 2.0 ? 2.0 ? ns clock to output in low-z tlz 1 2.0 ? 2.0 ? 2.0 ? ns setup time ts 1.3 ? 1.4 ? 1.5 ? ns hold time th 0.3 ? 0.4 ? 0.5 ? ns clock high time tkh 1.0 ? 1.0 ? 1.3 ? ns clock low time tkl 1.2 ? 1.2 ? 1.5 ? ns clock to output in high-z thz 1 1.5 2.8 1.5 2.8 1.5 3.0 ns g to output valid toe ? 2.8 ? 2.8 ? 3.0 ns g to output in low-z tolz 1 0 ? 0 ? 0 ? ns g to output in high-z tohz 1 ? 2.8 ? 2.8 ? 3.0 ns zz setup time tzzs 2 5 ? 5 ? 5 ? ns zz hold time tzzh 2 1 ? 1 ? 1 ? ns zz recovery tzzr 20 ? 20 ? 20 ? ns
GS816272Cc-333/300/250 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 9/2004 16/31 ? 2004, gsi technology pipeline mode timing (scd) begin read a cont cont deselect write b read c read c+1 read c+2 read c+3 cont deselect thz tkqx tkq tlz th ts tohz toe th ts th ts th ts th ts th ts ts th ts th ts th ts burst read burst read single write tkc tkc tkl tkl tkh single write single read tkh single read q(a) d(b) q(c) q(c+1) q(c+2) q(c+3) abc deselected with e1 e1 masks adsp e2 and e3 only sampled with adsp and adsc adsc initiated read ck adsp adsc adv a0?an gw bw ba ?bd e1 e2 e3 g dqa?dqd
GS816272Cc-333/300/250 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 9/2004 17/31 ? 2004, gsi technology flow through mode timing (scd) begin read a cont cont write b read c read c+1 read c+2 read c+3 read c cont deselect thz tkqx tkq tlz th ts tohz toe th ts th ts th ts th ts th ts th ts th ts th ts th ts th ts tkc tkc tkl tkl tkh tkh abc q(a) d(b) q(c) q(c+1) q(c+2) q(c+3) q(c) e2 and e3 only sampled with adsc adsc initiated read deselected with e1 fixed high ck adsp adsc adv a0?an gw bw ba ?bd e1 e2 e3 g dqa?dqd
GS816272Cc-333/300/250 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 9/2004 18/31 ? 2004, gsi technology pipeline mode timing (dcd) begin read a cont deselect deselect write b read c read c+1 read c+2 read c+3 cont deselect deselect thz tkqx tkq tlz th ts tohz toe th ts th ts th ts th ts th ts ts th ts th ts th ts tkc tkc tkl tkl tkh tkh q(a) d(b) q(c) q(c+1) q(c+2) q(c+3) abc hi-z deselected with e1 e2 and e3 only sampled with adsc adsc initiated read ck adsp adsc adv ao?an gw bw ba ?bd e1 e2 e3 g dqa?dqd
GS816272Cc-333/300/250 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 9/2004 19/31 ? 2004, gsi technology flow through m ode timing (dcd) begin read a cont deselect write b read c read c+1 read c+2 read c+3 read c deselect thz tkqx tlz th ts tohz toe tkq th ts th ts th ts th ts th ts th ts th ts th ts th ts th ts th ts tkc tkc tkl tkl tkh tkh abc q(a) d(b) q(c) q(c+1) q(c+2) q(c+3) q(c) e2 and e3 only sampled with adsp and adsc e1 masks adsp adsc initiated read deselected with e1 e1 masks adsp fixed high ck adsp adsc adv ao?an gw bw ba ?bd e1 e2 e3 g dqa?dqd
GS816272Cc-333/300/250 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 9/2004 20/31 ? 2004, gsi technology sleep mode during normal operation, zz must be pulled low, either by the us er or by its internal pull down resistor. when zz is pulled hig h, the sram will enter a power sleep mode after 2 cycles. at this time, internal stat e of the sram is preserved. when zz returns t o low, the sram operates normally after zz recovery time. sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to i sb 2. the duration of sleep mode is dictated by the length of time the zz is in a high state. after entering sleep mode, all inputs except zz become disabled and all outputs go to high-z the zz pin is an async hronous, active high input that cau ses the device to enter sleep mo de. when the zz pin is driven high, i sb 2 is guaranteed after the time tzzi is met. because zz is an asynchronous input, pending operations or operations in progress may not be properly completed if zz is asserted. therefore, sleep mode must not be initiat ed until valid pending operations are completed. similarly, when exitin g sleep mode during tzzr, only a deselect or read commands may be applied while the sram is recovering from sleep mode. sleep mode timing application tips single and dual cycle deselect scd devices (like this one) force the use of ?dummy read cycles? (read cycles that are launched nor mally, but that are ended wi th the output drivers inactive) in a fully synchronous environment. dummy read cycles waste perf ormance, but their use usually assures there will be no bus c ontention in transitions from reads to writes or between banks of rams. dcd srams do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings), but greater care mu st be exercised to avoid excessive bus contention. tzzr tzzh tzzs hold setup tkl tkl tkh tkh tkc tkc ck adsp adsc zz
GS816272Cc-333/300/250 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 9/2004 21/31 ? 2004, gsi technology jtag port operation overview the jtag port on this ram operates in a manner that is compliant with ieee standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as jtag). the jtag port input inte rface levels scale with v dd . the jtag output drivers are powered by v ddq . disabling the jtag port it is possible to use this device without utilizing the jtag port. the port is reset at power-up and will remain inactive unles s clocked. tck, tdi, and tms are designed with internal pull-up circuits.to assure normal operation of the ram with the jtag port unused, tck, tdi, and tms may be left floating or tied to either v dd or v ss . tdo should be left unconnected. jtag port registers overview the various jtag registers, refered to as test access port ortap registers, are select ed (one at a time) via the sequences of 1 s and 0s applied to tms as tck is strobed. each of the tap regist ers is a serial shift register that captures serial input data o n the rising edge of tck and pushes serial data out on the next falling edge of tck. when a register is selected, it is placed betwe en the tdi and tdo pins. instruction register the instruction register holds the instructi ons that are executed by the ta p controller when it is moved into the run, test/idl e, or the various data register states. instructions are 3 bits long. th e instruction register can be lo aded when it is placed betwee n the tdi and tdo pins. the instruction register is automatically preloa ded with the idcode instruction at power-up or whenever the controller is placed in test-logic-reset state. bypass register the bypass register is a single bit register that can be placed between tdi and tdo. it allows serial test data to be passed th rough the ram?s jtag port to another device in the scan chain with as little delay as possible. boundary scan register the boundary scan register is a collection of flip flops that can be preset by the logic level found on the ram?s input or i/o pins. the flip flops are then daisy chained togeth er so the levels found can be shifted seri ally out of the jtag port?s tdo pin. the boundary scan register also includes a number of place holder flip fl ops (always set to a logic 1). the relationship between t he jtag pin descriptions pin pin name i/o description tck test clock in clocks all tap events. all i nputs are captured on the rising edge of tck and all outputs propagate from the falling edge of tck. tms test mode select in the tms input is sampled on the rising edge of tck. this is the command input for the tap controller state machine. an undriven tms input wi ll produce the same result as a logic one input level. tdi test data in in the tdi input is sampled on the rising edge of tck. this is the input side of the serial registers placed between tdi and tdo. the register pl aced between tdi and tdo is determined by the state of the tap controller state machine and the instruction that is currently loaded in the tap instruction register (refer to the tap controll er state diagram). an undriven tdi pin will produce the same result as a logic one input level. tdo test data out out output that is active depending on the state of the tap state machine. output changes in response to the falling edge of tck. this is the out put side of the serial registers placed between tdi and tdo. note: this device does not have a trst (tap rese t) pin. trst is optional in ieee 1149.1. the test-logic-reset state is entered while tms is held high for five rising edges of tck. the tap cont roller is also reset automaticly at power-up.
GS816272Cc-333/300/250 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 9/2004 22/31 ? 2004, gsi technology device pins and the bits in the boundary scan register is de scribed in the scan order table following. the boundary scan register, under the control of the tap contro ller, is loaded with the contents of the rams i/o ring when the controller is in capture-dr state and then is placed between the tdi and tdo pins when the controller is moved to shift- dr state. sample-z, sample/preload and extest instructions can be us ed to activate the boundary scan register. jtag tap block diagram identification (id) register the id register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in capture-dr state with the idcode command loaded in the instruction re gister. the code is loaded from a 32-bit on-chip rom. it describes various attributes of the ram as indicated below. the register is then placed between the tdi and tdo pins when th e controller is moved into shift- dr state. bit 0 in the register is the lsb and the first to reach tdo when shifting begins. instruction register id code register boundary scan register 0 1 2 0 31 30 29 1 2 0 bypass register tdi tdo tms tck test access port (tap) controller 108 1 0 control signals
GS816272Cc-333/300/250 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 9/2004 23/31 ? 2004, gsi technology tap controller instruction set overview there are two classes of instructions defined in the standard 1149.1-1990; the standard (public) instructions, and device speci fic (private) instructions. some public instructions are mandator y for 1149.1 compliance. optional public instructions must be implemented in prescribed ways. the tap on th is device may be used to monitor all inpu t and i/o pads, and can be used to load address, data or control signals into the ram or to preload the i/o buffers. when the tap controller is placed in captur e-ir state the two least significant bits of the instruction regi ster are loaded wit h 01. when the controller is moved to the shift-ir state the instructi on register is placed between tdi and tdo. in this state the de sired instruction is serially loaded through the tdi input (while the previous contents are shifted out at tdo). for all instructions , the tap executes newly loaded instruct ions only when the controller is moved to update-ir state. the tap instruction set for this device is listed in the following table. id register contents die revision code not used i/o configuration gsi technology jedec vendor id code presence register bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x72 xxxx0000000000001001000110110011 x36 xxxx0000000000001000000110110011 x18 xxxx0000000000001010000110110011
GS816272Cc-333/300/250 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 9/2004 24/31 ? 2004, gsi technology jtag tap controller state diagram instruction descriptions bypass when the bypass instruction is loaded in the instruction register the bypass regi ster is placed between tdi and tdo. this occurs when the tap controller is moved to the shift-dr state. this allows the boa rd level scan path to be shortened to facili- tate testing of other devices in the scan path. sample/preload sample/preload is a standard 1149.1 mandatory public in struction. when the sample / preload instruction is loaded in the instruction register, moving the tap controller into the capture-dr state loads the data in the rams input and i/o buffers into the boundary scan register. boundary scan regist er locations are not associated with an input or i/o pin, and are loaded with the default stat e identified in the boundary s can chain table at the end of th is section of the datasheet. beca use the ram clock is independent from the tap clock (tck) it is possible for the tap to attempt to capture the i/o ring contents while the input buffers are in transition (i.e. in a metastable state). although allowing the tap to sample metastable inputs w ill not harm the device, repeatable results cannot be expected. ram input signals must be stabilized for long enough to meet the taps input data capture set-up plus hold time (tts plus tth) . the rams clock inputs need not be paused for any other tap operation except capturing the i/o ring contents into the boundary s can register. moving the contro ller to shift-dr state then places the boundary scan register between the tdi and tdo pins. extest extest is an ieee 1149.1 mandatory public instruction. it is to be executed whenever the instru ction register is loaded with all logic 0s. the extest command does not block or override th e ram?s input pins; therefore, the ram?s internal state is still determined by its input pins. select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir test logic reset run test idle 0 0 1 0 1 1 0 0 1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 10 0 0 1 11 1
GS816272Cc-333/300/250 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 9/2004 25/31 ? 2004, gsi technology typically, the boundary scan re gister is loaded with the desired pattern of data with the sample/preload command. then the extest command is used to outp ut the boundary scan register?s contents, in parallel, on the ram?s data output drivers on the falling edge of tck when the controller is in the update-ir state. alternately, the boundary scan register may be loaded in parallel using the extest command. when the extest instruc- tion is selected, the sate of all the ram?s input and i/o pins, as well as the default values at scan register locations not as so- ciated with a pin, are transfer red in parallel into the boundary scan regist er on the rising edge of tck in the capture-dr state, the ram?s output pins drive out the value of the boundary scan register location with which each output pin is associ- ated. idcode the idcode instruction causes the id rom to be loaded into the id register when the controller is in capture-dr mode and places the id register between the tdi a nd tdo pins in shift-dr mode. the idcode instruction is the default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. sample-z if the sample-z instruction is loaded in the instruction register, all ram outputs are forced to an inactiv e drive state (high- z) and the boundary scan register is connected between tdi and t do when the tap controller is moved to the shift-dr state. rfu these instructions are reserved fo r future use. in this device they replicate the bypass instruction.
GS816272Cc-333/300/250 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 9/2004 26/31 ? 2004, gsi technology jtag tap instruction set summary instruction code description notes extest 000 places the boundary scan register between tdi and tdo. 1 idcode 001 preloads id register and places it between tdi and tdo. 1, 2 sample-z 010 captures i/o ring contents. places the b oundary scan register between tdi and tdo. forces all ram output drivers to high-z. 1 rfu 011 do not use this instruction; reserved for future use. replicates bypass instruction. places bypass register between tdi and tdo. 1 sample/ preload 100 captures i/o ring contents. places the b oundary scan register between tdi and tdo. 1 gsi 101 gsi private instruction. 1 rfu 110 do not use this instruction; reserved for future use. replicates bypass instruction. places bypass register between tdi and tdo. 1 bypass 111 places bypass regist er between tdi and tdo. 1 notes: 1. instruction codes expressed in binary, msb on left, lsb on right. 2. default instruction automatically loaded at power-up and in test-logic-reset state. notes: 1. include scope and jig capacitance. 2. test conditions as as shown unless otherwise noted. jtag port ac test conditions parameter conditions input high level v dd ? 0.2 v input low level 0.2 v input slew rate 1 v/ns input reference level v ddq /2 output reference level v ddq /2 dq v ddq /2 50 ? 30pf * jtag port ac test load * distributed test jig capacitance
GS816272Cc-333/300/250 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 9/2004 27/31 ? 2004, gsi technology jtag port timing diagram jtag port recommended operating conditions and dc characteristics parameter symbol min. max. unit notes 3.3 v test port input high voltage v ihj3 2.0 v dd3 +0.3 v1 3.3 v test port input low voltage v ilj3 ? 0.3 0.8 v 1 2.5 v test port input high voltage v ihj2 0.6 * v dd2 v dd2 +0.3 v1 2.5 v test port input low voltage v ilj2 ? 0.3 0.3 * v dd2 v1 tms, tck and tdi input leakage current i inhj ? 300 1 ua 2 tms, tck and tdi input leakage current i inlj ? 1 100 ua 3 tdo output leakage current i olj ? 11ua4 test port output high voltage v ohj 1.7 ? v5, 6 test port output low voltage v olj ? 0.4 v 5, 7 test port output cmos high v ohjc v ddq ? 100 mv ? v5, 8 test port output cmos low v oljc ? 100 mv v 5, 9 notes: 1. input under/overshoot voltage must be ? 2 v > vi < v ddn +2 v not to exceed 4.6 v maximum, with a pulse width not to exceed 20% ttkc. 2. v ilj v in v ddn 3. 0 v v in v iljn 4. output disable, v out = 0 to v ddn 5. the tdo output driver is served by the v ddq supply. 6. i ohj = ? 4 ma 7. i olj = + 4 ma 8. i ohjc = ?100 ua 9. i ohjc = +100 ua tth tts ttkq tth tts tth tts ttkl ttkl ttkh ttkh ttkc ttkc tck tdi tms tdo parallel sram input
GS816272Cc-333/300/250 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 9/2004 28/31 ? 2004, gsi technology boundary scan (bsdl files) for information regarding the boundary scan chain, or to obta in bsdl files for this part, please contact our applications engineering department at: apps@gsitechnology.com . jtag port ac electrical characteristics parameter symbol min max unit tck cycle time ttkc 50 ? ns tck low to tdo valid ttkq ? 20 ns tck high pulse width ttkh 20 ? ns tck low pulse width ttkl 20 ? ns tdi & tms set up time tts 10 ? ns tdi & tms hold time tth 10 ? ns
GS816272Cc-333/300/250 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 9/2004 29/31 ? 2004, gsi technology 209 bga package dr awing (package c) 14 mm x 22 mm body, 1.0 mm bump pitch, 11 x 19 bump array symbol min typ max units symbol min typ max units a ? ? 1.70 mm d1 ? 18.0 (bsc) ? mm a1 0.40 0.50 0.60 mm e 13.9 14.0 14.1 mm ? b 0.50 0.60 0.70 mm e1 ? 10.0 (bsc) ? mm c 0.31 0.36 0.38 mm e ? 1.00 (bsc) ? mm d 21.9 22.0 22.1 mm aaa ?0.15? mm rev 1.0 a a1 c ? b e e e e1 d1 d aaa bottom view side view
GS816272Cc-333/300/250 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 9/2004 30/31 ? 2004, gsi technology ordering information for gs i synchronous burst rams org part number 1 type package speed 2 (mhz/ns) t a 3 status 256k x 72 GS816272Cc-333 pipeline/flow through 209 bga 333/4.5 c 256k x 72 GS816272Cc-300 pipeline/flow through 209 bga 300/5 c 256k x 72 GS816272Cc-250 pipeline/flow through 209 bga 250/5.5 c 256k x 72 GS816272Cc-333i pipeline/flow through 209 bga 333/4.5 i 256k x 72 GS816272Cc-30i pipeline/flow through 209 bga 300/5 i 256k x 72 GS816272Cc-250i pipeline/flow through 209 bga 250/5.5 i notes: 1. customers requiring delivery in tape and r eel should add the character ?t? to the end of the part number. example: gs816236cc -250it. 2. the speed column indicates the cycle frequenc y (mhz) of the device in pipeline mode and the latency (ns) in flow through mod e. each device is pipeline/flow through mode-selectable by the user. 3. t a = c = commercial temperature range. t a = i = industrial temperature range. 4. gsi offers other versions this type of device in many different configurations and with a variety of different features, onl y some of which are covered in this data sheet. see the gs i technology web site (www.gsitechnology.com ) for a complete listing of current offerings
GS816272Cc-333/300/250 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 9/2004 31/31 ? 2004, gsi technology 18mb sync sram datasheet revision history ds/daterev. code: old; new types of changes format or content page;revisions;reason 8162xxc_r1 ? creation of new datasheet

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